The present invention relates to noise-shaping digital amplifiers, and specifically to techniques for using and generating multiple and independent clocks in such amplifiers. It should be noted at the outset that although the invention is described herein with reference to a bandpass (e.g., RF) implementation, the present invention is also applicable to other amplifier configurations such as, for example, baseband audio amplifiers and motor drive circuits.
FIG. 1 shows an RF bandpass noise-shaping amplifier 100 designed according to techniques described in U.S. Pat. No. 5,777,512 for METHOD AND APPARATUS FOR OVERSAMPLED, NOISE-SHAPING, MIXED-SIGNAL PROCESSING issued Jul. 7, 1998, the entire disclosure of which is incorporated herein by reference for all purposes. RF amplifier 100 includes a frequency selective network 102 which, using continuous-time feedback, noise shapes the modulated RF input. Network 102 comprises at least one resonator stage having a transfer function designed to pass a band centered around 900 MHz.
A/D converter 104 converts the noise shaped RF signal to digital data using a sampling frequency fs which, in this example, is 3.6 GHz. A/D converter 104 may comprise a comparator.
Gate drive circuitry 106 takes the pulse train from A/D converter 104 and generates gate drive for each of FETs 108 and 110 of the power output stage of amplifier 100. The output power stage shown includes three inductors L1, L2 and L3, and capacitor C1. This configuration creates two separate resonances at nodes A and B respectively when the corresponding one of FETs 108 and 110 is off.
The continuous-time feedback to frequency selective network 102 is provided via feedback path 112. The output signal of the power stage is passed to a matching network 114 which passes the output RF signal to antenna 116 for transmission.
As will be understood, the amplifier configuration of FIG. 1 allows for two quantization states. With two quantization states there is a high number of signal transitions resulting in high drive losses. Therefore, it is desirable to provide techniques by which such losses may be mitigated or eliminated.
According to the present invention, an amplifier architecture is provided in which multi-level switching is enabled. That is, the amplifier architecture described herein exhibits more than two quantization states. This is achieved, in part, with parallel signal paths each of which has its own sampling circuitry. The multiple quantization states includes a state in which there is no signal output, thereby avoiding the undesirable switching losses described above. According to a specific embodiment, the clock signals for the different sampling circuits are independently developed resulting in a variety of other advantages.
Thus, the present invention provides an electronic device which includes at least two sampling circuits, and at least two switching stages configured in parallel. Each of the switching stages is coupled to one of the sampling circuits. The sampling circuits and the switching stages enable the electronic device to exhibit more than two quantization states. The electronic device further includes clock generation circuitry for generating independent clock signals for each of the sampling circuits.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.